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Error probability in synchronous digital circuits due to power supply noise
dc.contributor.author | Martorell Cid, Ferran |
dc.contributor.author | Pons Solé, Marc |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2008-01-15T12:01:06Z |
dc.date.available | 2008-01-15T12:01:06Z |
dc.date.created | 2007-07 |
dc.date.issued | 2007-09 |
dc.identifier.citation | Martorell, F.; Pons, M.; Rubio, A.; Moll, F. Error probability in synchronous digital circuits due to power supply noise. Design & technology of integrated systems 2007. |
dc.identifier.isbn | 1-4244-1278-1 |
dc.identifier.uri | http://hdl.handle.net/2117/1480 |
dc.description.abstract | This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality. |
dc.language.iso | eng |
dc.relation.ispartof | International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'07) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Processadors digitals |
dc.subject.lcsh | Integrated circuits Very large scale integration |
dc.subject.lcsh | Integrated circuits Very large scale integration Reliability |
dc.subject.other | Power supply noise |
dc.subject.other | Error probability |
dc.subject.other | CMOS synchronous circuits |
dc.title | Error probability in synchronous digital circuits due to power supply noise |
dc.type | Conference report |
dc.subject.lemac | Circuits digitals -- Disseny i construcció |
dc.subject.lemac | Circuits integrats a molt gran escala -- Disseny i construcció |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.date.end | 2007-09-05 |
dc.date.start | 2007-09-02 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Open Access |
local.personalitzacitacio | true |