Design issues of the multilevel active-clamped converter

Abstract

This paper studies several design issues of the multilevel active-clamped (MAC) topology. Several guidelines are proposed to guarantee a proper MAC converter design and improve its performance. The inclusion of a resistor network to balance the blocking voltage of devices when the converter is in OFF state, the use of self-powered gate-driver power-supplies, or the definition of a shut-down sequence to avoid possible device failures are some of the proposals. This paper also studies the singular device current spikes that appear in the MAC topology during switching state transitions. These spikes occur owing to diode reverse recovery and to the discharging of the device output parasitic capacitances. A proper device selection reduces these current peaks, decreasing the switching losses and the converter electromagnetic interference. Experimental tests are carried out with a four-level MAC prototype to validate the analysis.