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dc.contributor.authorAymerich Capdevila, Nivard
dc.contributor.authorGanapathy, Shrikanth
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2012-01-09T16:07:39Z
dc.date.available2012-01-09T16:07:39Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationAymerich, N. [et al.]. Impact of positive bias temperature instability (PBTI). A: ACM Great Lakes Symposium on VLSI. "Proceedings of the 2011 Great Lakes Symposium on VLSI". Lausanne: 2011, p. 227-282.
dc.identifier.isbn978-1-4503-0667-6
dc.identifier.urihttp://hdl.handle.net/2117/14433
dc.description.abstractMemory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level.
dc.format.extent56 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshMemory management (Computer science)
dc.subject.lcshDevice degradation
dc.titleImpact of positive bias temperature instability (PBTI)
dc.typeConference report
dc.subject.lemacMemòria -- Gestió -- Informàtica
dc.subject.lemacComponents electrònics -- Proves
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1145/1973009.1973065
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac8882848
dc.description.versionPostprint (published version)
local.citation.authorAymerich, N.; Ganapathy, S.; Rubio, J.; Canal, R.; González, A.
local.citation.contributorACM Great Lakes Symposium on VLSI
local.citation.pubplaceLausanne
local.citation.publicationNameProceedings of the 2011 Great Lakes Symposium on VLSI
local.citation.startingPage227
local.citation.endingPage282


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