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dc.contributor.authorGarcía Leyva, Lancelot
dc.contributor.authorAndrade Miceli, Dennis Michael
dc.contributor.authorGómez Fernández, Sergio
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2011-12-13T11:15:31Z
dc.date.available2011-12-13T11:15:31Z
dc.date.created2011-12
dc.date.issued2011-12
dc.identifier.citationGarcía, L. [et al.]. New redundant logic design concept for high noise and low voltage scenarios. "Microelectronics journal", Desembre 2011, vol. 42, núm. 12, p. 1359-1369.
dc.identifier.issn0026-2692
dc.identifier.urihttp://hdl.handle.net/2117/14228
dc.description.abstractThis paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the out put of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two’s complement 8x8-bit pipelined Baugh–Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0%errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes.
dc.format.extent11 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
dc.subject.lcshTurtle Logic
dc.titleNew redundant logic design concept for high noise and low voltage scenarios
dc.typeArticle
dc.subject.lemacMicroelectrònica -- Models matemàtics
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1016/j.mejo.2011.09.007
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S0026269211001960
dc.rights.accessRestricted access - publisher's policy
drac.iddocument8786583
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/120003/EU/MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems/MODERN
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
upcommons.citation.authorGarcía, L.; Andrade, D.; Gómez, S.; Calomarde, A.; Moll, F.; Rubio, J.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameMicroelectronics journal
upcommons.citation.volume42
upcommons.citation.number12
upcommons.citation.startingPage1359
upcommons.citation.endingPage1369


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