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dc.contributor.authorSoto, Javier
dc.contributor.authorMoreno Aróstegui, Juan Manuel
dc.contributor.authorCabestany Moncusí, Joan
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2011-11-18T19:18:28Z
dc.date.available2011-11-18T19:18:28Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationSoto, J.; Moreno, J.; Cabestany, J. Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities. A: International Work-Conference on Artificial Neural Networks. "11th International Work-Conference on Artificial Neural Networks". Torremolinos: Springer Verlag, 2011, p. 557-564.
dc.identifier.isbn0302-9743
dc.identifier.urihttp://hdl.handle.net/2117/13973
dc.description.abstractThis paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherSpringer Verlag
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer architecture
dc.titleDescription of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities
dc.typeConference report
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades
dc.identifier.doi10.1007/978-3-642-21498-1_70
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
drac.iddocument8647281
dc.description.versionPostprint (published version)
upcommons.citation.authorSoto, J.; Moreno, J.; Cabestany, J.
upcommons.citation.contributorInternational Work-Conference on Artificial Neural Networks
upcommons.citation.pubplaceTorremolinos
upcommons.citation.publishedtrue
upcommons.citation.publicationName11th International Work-Conference on Artificial Neural Networks
upcommons.citation.startingPage557
upcommons.citation.endingPage564


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