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A new probabilistic design methodology of nanoscale digital circuits
dc.contributor.author | García Leyva, Lancelot |
dc.contributor.author | Calomarde Palomino, Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2011-10-27T13:49:35Z |
dc.date.available | 2011-10-27T13:49:35Z |
dc.date.created | 2011 |
dc.date.issued | 2011 |
dc.identifier.citation | García, L. [et al.]. A new probabilistic design methodology of nanoscale digital circuits. A: International Conference on Electrical Communications and Computers. "21st. International Conference on Electrical Communications and Computers". San Andres Cholula, Puebla: IEEE Press. Institute of Electrical and Electronics Engineers, 2011, p. 190-193. |
dc.identifier.uri | http://hdl.handle.net/2117/13684 |
dc.description.abstract | The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | IEEE Press. Institute of Electrical and Electronics Engineers |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject.lcsh | Integrated circuits -- Design and construction |
dc.subject.lcsh | Nanoelectromechanical systems |
dc.subject.lcsh | Nanoscale digital circuits |
dc.title | A new probabilistic design methodology of nanoscale digital circuits |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats |
dc.subject.lemac | Nanotecnologia -- Aplicacions |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/CONIELECOMP.2011.5749358 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 6066734 |
dc.description.version | Postprint (published version) |
local.citation.author | García, L.; Calomarde, A.; Moll, F.; Rubio, J. |
local.citation.contributor | International Conference on Electrical Communications and Computers |
local.citation.pubplace | San Andres Cholula, Puebla |
local.citation.publicationName | 21st. International Conference on Electrical Communications and Computers |
local.citation.startingPage | 190 |
local.citation.endingPage | 193 |