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dc.contributor.authorGarcía Leyva, Lancelot
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2011-10-27T13:49:35Z
dc.date.available2011-10-27T13:49:35Z
dc.date.created2011
dc.date.issued2011
dc.identifier.citationGarcía, L. [et al.]. A new probabilistic design methodology of nanoscale digital circuits. A: International Conference on Electrical Communications and Computers. "21st. International Conference on Electrical Communications and Computers". San Andres Cholula, Puebla: IEEE Press. Institute of Electrical and Electronics Engineers, 2011, p. 190-193.
dc.identifier.urihttp://hdl.handle.net/2117/13684
dc.description.abstractThe continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs.
dc.format.extent4 p.
dc.language.isoeng
dc.publisherIEEE Press. Institute of Electrical and Electronics Engineers
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject.lcshIntegrated circuits -- Design and construction
dc.subject.lcshNanoelectromechanical systems
dc.subject.lcshNanoscale digital circuits
dc.titleA new probabilistic design methodology of nanoscale digital circuits
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.subject.lemacNanotecnologia -- Aplicacions
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/CONIELECOMP.2011.5749358
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac6066734
dc.description.versionPostprint (published version)
local.citation.authorGarcía, L.; Calomarde, A.; Moll, F.; Rubio, J.
local.citation.contributorInternational Conference on Electrical Communications and Computers
local.citation.pubplaceSan Andres Cholula, Puebla
local.citation.publicationName21st. International Conference on Electrical Communications and Computers
local.citation.startingPage190
local.citation.endingPage193


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