Dynamic selection and update of digital predistorter coefficients for power amplifier linearization
Document typeConference lecture
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
In this paper, a new method for dynamically estimating and updating the coefficients of a digital predistortion (DPD) linearizer is presented. By means of the partial least squares (PLS) algorithm, the basis matrix used in the DPD estimation/adaptation is dynamically updated at every iteration to minimize the linearization error. Moreover, only the minimum necessary DPD coefficients being required to meet a target estimation error are computed. The proposed estimation technique is compared with the standard least squares (LS) estimation solved by using QR decomposition. Experimental results show the similar linearization performance obtained with both estimation methods, but in the case of the dynamic PLS, less coefficients are used at every iteration. Finally, the proposed algorithm allows a high level of parallelization, which makes it suitable for FPGA implementation. © 2019 IEEE.
CitationPham, T. [et al.]. Dynamic selection and update of digital predistorter coefficients for power amplifier linearization. A: IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications. "2019 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications (PAWR)". Institute of Electrical and Electronics Engineers (IEEE), p. 1-4.
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