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dc.contributor.authorCortadella, Jordi
dc.contributor.authorKishinevsky, Michael
dc.contributor.authorKondratyev, Alex
dc.contributor.authorLavagno, Luciano
dc.contributor.authorTaubin, Alexander
dc.contributor.authorYakovlev, Alex
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-06-03T09:05:16Z
dc.date.available2019-06-03T09:05:16Z
dc.date.issued1998
dc.identifier.citationCortadella, J. [et al.]. Lazy transition systems: application to timing optimization of asynchronous circuits. A: IEEE/ACM International Conference on Computer-Aided Design. "1998 InternationaI Conference on Computer-Aided Design: November 8-12, 1998, San Jose, California: digest of technical papers". Institute of Electrical and Electronics Engineers (IEEE), 1998, p. 324-331.
dc.identifier.isbn1-58113-008-2
dc.identifier.urihttp://hdl.handle.net/2117/133832
dc.description.abstractThe paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents necessary conditions to synthesize circuits with a correct behavior under the given timing assumptions. Preliminary results show that significant area and performance improvements can be obtained by exploiting the extra "don't care" space implicitly provided by the laziness of the events.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.lcshLogic design
dc.subject.otherDelay
dc.subject.otherTiming
dc.subject.otherCircuit synthesis
dc.subject.otherSwitches
dc.subject.otherPermission
dc.subject.otherWire
dc.subject.otherSwitching circuits
dc.subject.otherDesign methodology
dc.subject.otherConcurrent computing
dc.titleLazy transition systems: application to timing optimization of asynchronous circuits
dc.typeConference report
dc.subject.lemacCircuits asíncrons
dc.subject.lemacEstructura lògica
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1145/288548.288633
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://dl.acm.org/citation.cfm?id=288548.288633
dc.rights.accessOpen Access
drac.iddocument2356669
dc.description.versionPostprint (author's final draft)
upcommons.citation.authorCortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Taubin, A.; Yakovlev, A.
upcommons.citation.contributorIEEE/ACM International Conference on Computer-Aided Design
upcommons.citation.publishedtrue
upcommons.citation.publicationName1998 InternationaI Conference on Computer-Aided Design: November 8-12, 1998, San Jose, California: digest of technical papers
upcommons.citation.startingPage324
upcommons.citation.endingPage331


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