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Time-constrained loop pipelining
dc.contributor.author | Sánchez Carracedo, Fermín |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2019-05-24T11:18:51Z |
dc.date.available | 2019-05-24T11:18:51Z |
dc.date.issued | 2005 |
dc.identifier.citation | Sánchez, F.; Cortadella, J. Time-constrained loop pipelining. A: IEEE/ACM International Conference on Computer-Aided Design. "Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995: San Jose, California, USA, November 5-9, 1995". Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 592-596. |
dc.identifier.isbn | 0-8186-7213-7 |
dc.identifier.uri | http://hdl.handle.net/2117/133457 |
dc.description.abstract | This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on dividing the problem into two simpler and independent tasks: retiming and scheduling. TCLP explores different sets of resources, searching for a maximum resource utilization. This reduces area requirements. After a minimum set of resources has been found, the execution throughput is increased and the number of registers required by the loop schedule is reduced. TCLP attempts to generate a schedule which minimizes cost in time and area (resources and registers). The results show that TCLP obtains optimal schedules in most cases. |
dc.format.extent | 5 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Informàtica teòrica |
dc.subject.lcsh | Microprocessors -- Programming |
dc.subject.lcsh | Parallel algorithms |
dc.subject.other | Pipeline processing |
dc.subject.other | Throughput |
dc.subject.other | Processor scheduling |
dc.subject.other | Iron |
dc.subject.other | Computer architecture |
dc.subject.other | Resource management |
dc.subject.other | Costs |
dc.subject.other | Timing |
dc.subject.other | Delay effects |
dc.subject.other | Registers |
dc.title | Time-constrained loop pipelining |
dc.type | Conference report |
dc.subject.lemac | Microprocessadors -- Programació |
dc.subject.lemac | Algorismes paral·lels |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ICCAD.1995.480177 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/480177 |
dc.rights.access | Open Access |
local.identifier.drac | 2376183 |
dc.description.version | Postprint (published version) |
local.citation.author | Sánchez, F.; Cortadella, J. |
local.citation.contributor | IEEE/ACM International Conference on Computer-Aided Design |
local.citation.publicationName | Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995: San Jose, California, USA, November 5-9, 1995 |
local.citation.startingPage | 592 |
local.citation.endingPage | 596 |