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dc.contributor.authorSánchez Carracedo, Fermín
dc.contributor.authorCortadella, Jordi
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-05-24T11:18:51Z
dc.date.available2019-05-24T11:18:51Z
dc.date.issued2005
dc.identifier.citationSánchez, F.; Cortadella, J. Time-constrained loop pipelining. A: IEEE/ACM International Conference on Computer-Aided Design. "Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995: San Jose, California, USA, November 5-9, 1995". Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 592-596.
dc.identifier.isbn0-8186-7213-7
dc.identifier.urihttp://hdl.handle.net/2117/133457
dc.description.abstractThis paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on dividing the problem into two simpler and independent tasks: retiming and scheduling. TCLP explores different sets of resources, searching for a maximum resource utilization. This reduces area requirements. After a minimum set of resources has been found, the execution throughput is increased and the number of registers required by the loop schedule is reduced. TCLP attempts to generate a schedule which minimizes cost in time and area (resources and registers). The results show that TCLP obtains optimal schedules in most cases.
dc.format.extent5 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Informàtica teòrica
dc.subject.lcshMicroprocessors -- Programming
dc.subject.lcshParallel algorithms
dc.subject.otherPipeline processing
dc.subject.otherThroughput
dc.subject.otherProcessor scheduling
dc.subject.otherIron
dc.subject.otherComputer architecture
dc.subject.otherResource management
dc.subject.otherCosts
dc.subject.otherTiming
dc.subject.otherDelay effects
dc.subject.otherRegisters
dc.titleTime-constrained loop pipelining
dc.typeConference report
dc.subject.lemacMicroprocessadors -- Programació
dc.subject.lemacAlgorismes paral·lels
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/ICCAD.1995.480177
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/480177
dc.rights.accessOpen Access
drac.iddocument2376183
dc.description.versionPostprint (published version)
upcommons.citation.authorSánchez, F.; Cortadella, J.
upcommons.citation.contributorIEEE/ACM International Conference on Computer-Aided Design
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995: San Jose, California, USA, November 5-9, 1995
upcommons.citation.startingPage592
upcommons.citation.endingPage596


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