Physical-aware link allocation and route assignment for chip multiprocessing
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and the message routes for the traffic among the processing elements of the system. The solution of the problem meets the physical and performance constraints defined by the designer. The method guarantees that the generated solution is deadlock free. It is also capable of automatically discovering topologies that have been previously used in industrial systems. The applicability of the method has been validated by solving realistic size interconnect networks modeling the typical multiprocessor systems.
CitationNikitin, N. [et al.]. Physical-aware link allocation and route assignment for chip multiprocessing. A: IEEE/ACM International Symposium on Networks-on-Chip. "The Fourth ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2010: 3-6 May 2010, Grenoble, France: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 125-134.