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dc.contributor.authorChronaki, Kallia
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorCasas, Marc
dc.contributor.authorRico, Alejandro
dc.contributor.authorBadia Sala, Rosa Maria
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2019-05-24T08:03:10Z
dc.date.issued2019-05-01
dc.identifier.citationChronaki, K. [et al.]. On the maturity of parallel applications for asymmetric multi-core processors. "Journal of parallel and distributed computing", 1 Maig 2019, vol. 127, p. 105-115.
dc.identifier.issn0743-7315
dc.identifier.urihttp://hdl.handle.net/2117/133416
dc.description.abstractAsymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility power budget. This paper performs the first extensive evaluation of how portable are the current HPC applications for such supercomputing systems. Specifically we evaluate several execution models on an ARM big.LITTLE AMC using the PARSEC benchmark suite that includes representative highly parallel applications. We compare schedulers at the user, OS and runtime levels, using both static and dynamic options and multiple configurations, and assess the impact of these options on the well-known problem of balancing the load across AMCs. Our results demonstrate that scheduling is more effective when it takes place in the runtime system level as it improves the baseline by 23%, while the heterogeneous-aware OS scheduling solution improves the baseline by 10%.
dc.description.sponsorshipThis work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), and by the European Union's Horizon 2020 research and innovation programme under grant agreement No 671697 and No. 779877. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal fellowship number RYC-2016-21104.
dc.format.extent11 p.
dc.language.isoeng
dc.publisherElsevier
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshSupercomputers
dc.subject.lcshHigh performance computing
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherScheduling
dc.subject.otherRuntime systems
dc.subject.otherAsymmetric multi-cores
dc.subject.otherHPC
dc.titleOn the maturity of parallel applications for asymmetric multi-core processors
dc.typeArticle
dc.subject.lemacSuperordinadors
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1016/j.jpdc.2019.01.007
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://www.sciencedirect.com/science/article/pii/S0743731519300267
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac24470457
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/AEI/RYC-2016-21104
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1051
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1272
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology/Mont-Blanc 3
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/779877/EU/Mont-Blanc 2020, European scalable, modular and power efficient HPC processor/Mont-Blanc 2020
dc.date.lift2021-01-19
local.citation.authorChronaki, K.; Moreto, M.; Casas, M.; Rico, A.; Badia, R.M.; Ayguade, E.; Valero, M.
local.citation.publicationNameJournal of parallel and distributed computing
local.citation.volume127
local.citation.startingPage105
local.citation.endingPage115
local.requestitem.embargattrue


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