A multi-radix approach to asynchronous division
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled data with data-dependent computation time. In this scheme the selection function is very simple and may be implemented using a fast adder This function speculates the result digit and, when the speculation is incorrect, a correction of the quotient and of the residual must be performed. When the residual satisfies some constraints it is also possible to switch to a higher radix, computing a fraction of the next digit in advance. This results in a division scheme with a variable iteration time and a variable number of iterations and hence with an asynchronous behaviour Several designs were realized and compared both in terms of execution time and area. The fastest unit considered is a radix-64 divider that may switch to radix 128 or 256. Our evaluations show that area /spl times/ delay savings from 25% to 65%, compared to equivalent synchronous designs, may be achieved.
CitationCornetta, G.; Cortadella, J. A multi-radix approach to asynchronous division. A: IEEE International Symposium on Asynchronous Circuits and Systems. "Seventh International Symposium on Asynchronous Circuits and Systems, ASYNC 2001: March 11-14, 2001, Salt Lake City, Utah: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 25-34.