Narrowing the margins with elastic clocks
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.
CitationCortadella, J. [et al.]. Narrowing the margins with elastic clocks. A: IEEE International Conference on Integrated Circuit Design and Technology. "2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT: MINATEC, Grenoble, France, June 2-June 4, 2010". Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 146-150.