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dc.contributor.authorSuárez, Dario
dc.contributor.authorMonreal Arnal, Teresa
dc.contributor.authorVallejo, Fernando
dc.contributor.authorBeivide Palacio, Julio Ramón
dc.contributor.authorViñals Yufera, Víctor
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2011-09-21T13:54:46Z
dc.date.available2011-09-21T13:54:46Z
dc.date.created2009
dc.date.issued2009
dc.identifier.citationSuárez, D. [et al.]. Light NUCA: a proposal for bridging the inter-cache latency gap. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe 2009". Nice: IEEE Computer Society, 2009, p. 530-535.
dc.identifier.urihttp://hdl.handle.net/2117/13287
dc.description.abstractTo deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). Recently, Non-Uniform Cache Architectures (NUCAs) have been proposed to sustain the size growth trend of secondary caches that is threatened by wire-delay problems. NUCAs are size-oriented, and they were not conceived to close the inter-cache latency gap. To tackle this problem, we propose Light NUCAs (L-NUCAs) leveraging on-chip wire density to interconnect small tiles through specialized networks, which convey packets with distributed and dynamic routing. Our design reduces the tile delay (cache access plus one-hop routing) to a single processor cycle and places cache lines at a finer-granularity than conventional caches reducing cache latency. Our evaluations show that in general, L-NUCA improves simultaneously performance, energy, and area when integrated into both conventional or D-NUCA hierarchies.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherIEEE Computer Society
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer storage devices
dc.subject.otherNon-uniform cache architectures
dc.subject.otherNUCAs
dc.subject.otherLight NUCAs
dc.subject.otherL-NUCAs
dc.titleLight NUCA: a proposal for bridging the inter-cache latency gap
dc.typeConference lecture
dc.subject.lemacOrdinadors -- Memòries
dc.rights.accessOpen Access
drac.iddocument2452375
dc.description.versionPostprint (author’s final draft)
upcommons.citation.authorSuárez, D.; Monreal, T.; Vallejo, F.; Beivide, R.; Viñals, V.
upcommons.citation.contributorDesign, Automation and Test in Europe
upcommons.citation.pubplaceNice
upcommons.citation.publishedtrue
upcommons.citation.publicationNameDesign, Automation and Test in Europe 2009
upcommons.citation.startingPage530
upcommons.citation.endingPage535


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