Light NUCA: a proposal for bridging the inter-cache latency gap
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Cita com:
hdl:2117/13287
Tipus de documentComunicació de congrés
Data publicació2009
EditorIEEE Computer Society
Condicions d'accésAccés obert
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continguts d'aquesta obra estan subjectes a la llicència de Creative Commons
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Reconeixement-NoComercial-SenseObraDerivada 3.0 Espanya
Abstract
To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them
and fast L1 caches (inter-cache latency gap). Recently, Non-Uniform Cache Architectures (NUCAs) have been proposed
to sustain the size growth trend of secondary caches that is threatened by wire-delay problems. NUCAs are size-oriented, and they were not conceived to close the inter-cache latency gap. To tackle this problem, we propose Light NUCAs (L-NUCAs) leveraging on-chip wire density to interconnect small tiles through specialized networks, which convey packets with distributed and dynamic routing. Our design reduces the tile delay (cache access plus one-hop routing) to a single processor cycle and places cache
lines at a finer-granularity than conventional caches reducing cache latency. Our evaluations show that in general, L-NUCA
improves simultaneously performance, energy, and area when integrated into both conventional or D-NUCA hierarchies.
CitacióSuárez, D. [et al.]. Light NUCA: a proposal for bridging the inter-cache latency gap. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe 2009". Nice: IEEE Computer Society, 2009, p. 530-535.
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