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An architectural journey into RISC architectures for HPC workloads
| dc.contributor | Ayguadé Parra, Eduard |
| dc.contributor | Mantovani, Filippo |
| dc.contributor.author | Xu Lin, Ying Hao |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2019-04-11T07:47:40Z |
| dc.date.available | 2019-04-11T07:47:40Z |
| dc.date.issued | 2019-01-28 |
| dc.identifier.uri | http://hdl.handle.net/2117/131610 |
| dc.description.abstract | The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V platform and 1 Open Source RISC-V core running in an FPGA have been tested. |
| dc.language.iso | eng |
| dc.publisher | Universitat Politècnica de Catalunya |
| dc.subject | Àrees temàtiques de la UPC::Informàtica |
| dc.subject.lcsh | Cluster |
| dc.subject.lcsh | High performance computing |
| dc.subject.other | RISC-V |
| dc.subject.other | FPGA |
| dc.subject.other | OmpSs |
| dc.subject.other | computació d'altes prestaciones |
| dc.subject.other | clusterització |
| dc.subject.other | programació heterogènia |
| dc.subject.other | high-performance computing |
| dc.subject.other | arm |
| dc.subject.other | clustering |
| dc.subject.other | heterogeneous programming |
| dc.title | An architectural journey into RISC architectures for HPC workloads |
| dc.type | Master thesis |
| dc.subject.lemac | Sistemes productius locals |
| dc.subject.lemac | Càlcul intensiu (Informàtica) |
| dc.identifier.slug | 140782 |
| dc.rights.access | Open Access |
| dc.date.updated | 2019-01-30T05:00:28Z |
| dc.audience.educationlevel | Màster |
| dc.audience.mediator | Facultat d'Informàtica de Barcelona |
| dc.audience.degree | MÀSTER UNIVERSITARI EN INNOVACIÓ I RECERCA EN INFORMÀTICA (Pla 2012) |
| dc.contributor.covenantee | Barcelona Supercomputing Center |
