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dc.contributorAyguadé Parra, Eduard
dc.contributorMantovani, Filippo
dc.contributor.authorXu Lin, Ying Hao
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-04-11T07:47:40Z
dc.date.available2019-04-11T07:47:40Z
dc.date.issued2019-01-28
dc.identifier.urihttp://hdl.handle.net/2117/131610
dc.description.abstractThe thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V platform and 1 Open Source RISC-V core running in an FPGA have been tested.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshCluster
dc.subject.lcshHigh performance computing
dc.subject.otherRISC-V
dc.subject.otherFPGA
dc.subject.otherOmpSs
dc.subject.othercomputació d'altes prestaciones
dc.subject.otherclusterització
dc.subject.otherprogramació heterogènia
dc.subject.otherhigh-performance computing
dc.subject.otherarm
dc.subject.otherclustering
dc.subject.otherheterogeneous programming
dc.titleAn architectural journey into RISC architectures for HPC workloads
dc.typeMaster thesis
dc.subject.lemacSistemes productius locals
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.identifier.slug140782
dc.rights.accessOpen Access
dc.date.updated2019-01-30T05:00:28Z
dc.audience.educationlevelMàster
dc.audience.mediatorFacultat d'Informàtica de Barcelona
dc.contributor.covenanteeBarcelona Supercomputing Centre


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