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dc.contributor.authorCastañer Muñoz, Luis María
dc.contributor.authorAlcubilla González, Ramón
dc.contributor.authorBenavent, A
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2019-04-03T16:44:26Z
dc.date.issued1994-12
dc.identifier.citationCastañer, L.; Alcubilla, R.; Benavent, A. Bipolar transistor vertical vertical scaling framework. "Solid-state electronics", Desembre 1994, vol. 38, núm. 7, p. 1367-1371.
dc.identifier.issn0038-1101
dc.identifier.urihttp://hdl.handle.net/2117/131231
dc.description.abstractScaling factors for current and transit time are derived for polysilicon emitter, silicon based heterojunction bipolar transistors. It is shown that a simple set of analytical equations in integral form can be used to analyse the above scaling properties and by introducing two “heterojunction factors” can be extended to the scaling analysis of heterojunction bipolar transistors.
dc.format.extent5 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subject.lcshTransistors
dc.titleBipolar transistor vertical vertical scaling framework
dc.typeArticle
dc.subject.lemacTransistors
dc.contributor.groupUniversitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies
dc.identifier.doi10.1016/0038-1101(94)00254-D
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://www.sciencedirect.com/science/article/pii/003811019400254D
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac690342
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorCastañer, L.; Alcubilla, R.; Benavent, A.
local.citation.publicationNameSolid-state electronics
local.citation.volume38
local.citation.number7
local.citation.startingPage1367
local.citation.endingPage1371


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