Bipolar transistor vertical vertical scaling framework

Castañer Muñoz, Luis María; Alcubilla González, Ramón; Benavent, A

doi:10.1016/0038-1101(94)00254-D

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Castañer Muñoz, Luis María

Alcubilla González, Ramón

Benavent, A

Document typeArticle

Defense date1994-12

Rights accessRestricted access - publisher's policy

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder

Abstract

Scaling factors for current and transit time are derived for polysilicon emitter, silicon based heterojunction bipolar transistors. It is shown that a simple set of analytical equations in integral form can be used to analyse the above scaling properties and by introducing two “heterojunction factors” can be extended to the scaling analysis of heterojunction bipolar transistors.

CitationCastañer, L.; Alcubilla, R.; Benavent, A. Bipolar transistor vertical vertical scaling framework. "Solid-state electronics", Desembre 1994, vol. 38, núm. 7, p. 1367-1371.

URIhttp://hdl.handle.net/2117/131231

DOI10.1016/0038-1101(94)00254-D

ISSN0038-1101

Publisher versionhttps://www.sciencedirect.com/science/article/pii/003811019400254D

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