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Simulating whole supercomputer applications
| dc.contributor.author | González García, Juan |
| dc.contributor.author | Casas, Marc |
| dc.contributor.author | Giménez Lucas, Judit |
| dc.contributor.author | Moretó Planas, Miquel |
| dc.contributor.author | Ramírez Bellido, Alejandro |
| dc.contributor.author | Labarta Mancho, Jesús José |
| dc.contributor.author | Valero Cortés, Mateo |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2011-08-25T11:09:46Z |
| dc.date.available | 2011-08-25T11:09:46Z |
| dc.date.created | 2011-06 |
| dc.date.issued | 2011-06 |
| dc.identifier.citation | González, J. [et al.]. Simulating whole supercomputer applications. "IEEE micro", Juny 2011, vol. 31, núm. 3, p. 32-45. |
| dc.identifier.issn | 0272-1732 |
| dc.identifier.uri | http://hdl.handle.net/2117/13117 |
| dc.description.abstract | Detailed simulations of large scale message-passing interface parallel applications are extremely time consuming and resource intensive. A new methodology that combines signal processing and data mining techniques plus a multilevel simulation reduces the simulated data by various orders of magnitude. This reduction makes possible detailed software performance analysis and accurate performance predictions in a reasonable time. |
| dc.format.extent | 14 p. |
| dc.language.iso | eng |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
| dc.subject.lcsh | Supercomputers -- Design and construction. |
| dc.title | Simulating whole supercomputer applications |
| dc.type | Article |
| dc.subject.lemac | Superordinadors -- Simulació per ordinador |
| dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.identifier.doi | 10.1109/MM.2011.58 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5875957&tag=1 |
| dc.rights.access | Restricted access - publisher's policy |
| local.identifier.drac | 5821790 |
| dc.description.version | Postprint (published version) |
| dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC |
| local.citation.author | González, J.; Casas, M.; Gimenez, J.; Moreto, M.; Alex Ramirez; Labarta, J.; Valero, M. |
| local.citation.publicationName | IEEE micro |
| local.citation.volume | 31 |
| local.citation.number | 3 |
| local.citation.startingPage | 32 |
| local.citation.endingPage | 45 |
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