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dc.contributor.authorVallejo, Enrique
dc.contributor.authorSanyal, Sutirtha
dc.contributor.authorHarris, Tim
dc.contributor.authorVallejo, Fernando
dc.contributor.authorBeivide, Ramón
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2011-08-25T09:51:58Z
dc.date.available2011-08-25T09:51:58Z
dc.date.created2011-06
dc.date.issued2011-06
dc.identifier.citationVallejo, E. [et al.]. Hybrid transactional memory with pessimistic concurrency control. "International journal of parallel programming", Juny 2011, vol. 39, núm. 3, p. 375-396.
dc.identifier.issn0885-7458
dc.identifier.urihttp://hdl.handle.net/2117/13110
dc.description.abstractTransactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being modified. Such implementations can suffer from the “privatization” problem, in which transactional and non-transactional accesses to the same location can lead to inconsistent results. One solution is the use of Pessimistic Concurrency Control, but it entails an important performance penalty due to the need of reader-writer locking. In this paper a hybrid TM design is proposed to reduce the performance overheads caused by the use of these locks while combining three desirable features: i) full TM functionality whether or not the architectural support is present; ii) execution of a single common code path in software or hardware; and, iii) immunity from the privatization problem. The analysis shows how a Hybrid TM can lose important properties, such as starvation freedom. To overcome this issue, Directory Reservations is presented, a low-cost mechanism improving existent solutions designed for Hardware TM.
dc.format.extent22 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer storage devices -- Design and construction
dc.subject.lcshHybrid transactional memory
dc.subject.lcshPessimistic concurrency control
dc.subject.lcshWriter starvation
dc.subject.lcshDirectory reservation
dc.titleHybrid transactional memory with pessimistic concurrency control
dc.typeArticle
dc.subject.lemacMemòria transaccional
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1007/s10766-010-0158-x
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://posgrado.escom.ipn.mx/biblioteca/Hybrid%20Transactional%20Memory%20with%20Pessimistic.pdf
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac5805922
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
local.citation.authorVallejo, E.; Sanyal, S.; Harris, T.; Vallejo, F.; Beivide, R.; Unsal, O.; Cristal-Kestelman, A.; Valero, M.
local.citation.publicationNameInternational journal of parallel programming
local.citation.volume39
local.citation.number3
local.citation.startingPage375
local.citation.endingPage396


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