Hybrid transactional memory with pessimistic concurrency control
Tipus de documentArticle
Condicions d'accésAccés restringit per política de l'editorial
Projecte de la Comissió EuropeaHIPEAC - High Performance and Embedded Architecture and Compilation (EC-FP7-217068)
Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being modified. Such implementations can suffer from the “privatization” problem, in which transactional and non-transactional accesses to the same location can lead to inconsistent results. One solution is the use of Pessimistic Concurrency Control, but it entails an important performance penalty due to the need of reader-writer locking. In this paper a hybrid TM design is proposed to reduce the performance overheads caused by the use of these locks while combining three desirable features: i) full TM functionality whether or not the architectural support is present; ii) execution of a single common code path in software or hardware; and, iii) immunity from the privatization problem. The analysis shows how a Hybrid TM can lose important properties, such as starvation freedom. To overcome this issue, Directory Reservations is presented, a low-cost mechanism improving existent solutions designed for Hardware TM.
CitacióVallejo, E. [et al.]. Hybrid transactional memory with pessimistic concurrency control. "International journal of parallel programming", Juny 2011, vol. 39, núm. 3, p. 375-396.
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