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Coping with the variability of combinational logic delays
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Kondratyev, Alex |
dc.contributor.author | Lavagno, Luciano |
dc.contributor.author | Sotiriou, Christos P. |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2019-03-28T08:36:15Z |
dc.date.available | 2019-03-28T08:36:15Z |
dc.date.issued | 2004 |
dc.identifier.citation | Cortadella, J. [et al.]. Coping with the variability of combinational logic delays. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "IEEE International Conference on Computer Design: VLSI in Computers & Processors, ICCD 2004: 11-13 October 2004, San Jose, CA: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 505-508. |
dc.identifier.isbn | 0-7695-2231-9 |
dc.identifier.uri | http://hdl.handle.net/2117/130966 |
dc.description.abstract | This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Asynchronous circuits |
dc.subject.lcsh | Logic circuits |
dc.subject.other | Clocks |
dc.subject.other | Timing |
dc.subject.other | Delay estimation |
dc.subject.other | Time measurement |
dc.subject.other | Delay effects |
dc.subject.other | Logic testing |
dc.subject.other | Combinational circuits |
dc.subject.other | Crosstalk |
dc.subject.other | Libraries |
dc.subject.other | Encoding |
dc.title | Coping with the variability of combinational logic delays |
dc.type | Conference report |
dc.subject.lemac | Circuits asíncrons |
dc.subject.lemac | Circuits lògics |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ICCD.2004.1347969 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/1347969 |
dc.rights.access | Open Access |
local.identifier.drac | 2337703 |
dc.description.version | Postprint (published version) |
local.citation.author | Cortadella, J.; Kondratyev, A.; Lavagno, L.; Sotiriou, C. P. |
local.citation.contributor | IEEE International Conference on Computer Design: VLSI in Computers and Processors |
local.citation.publicationName | IEEE International Conference on Computer Design: VLSI in Computers & Processors, ICCD 2004: 11-13 October 2004, San Jose, CA: proceedings |
local.citation.startingPage | 505 |
local.citation.endingPage | 508 |