Coping with the variability of combinational logic delays
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique.
CitationCortadella, J. [et al.]. Coping with the variability of combinational logic delays. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "IEEE International Conference on Computer Design: VLSI in Computers & Processors, ICCD 2004: 11-13 October 2004, San Jose, CA: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 505-508.