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dc.contributor.authorKam, Timothy
dc.contributor.authorKishinevsky, Michael
dc.contributor.authorCortadella, Jordi
dc.contributor.authorGalcerán Oms, Marc
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-03-28T08:14:12Z
dc.date.available2019-03-28T08:14:12Z
dc.date.issued2008
dc.identifier.citationKam, T. [et al.]. Correct-by-construction microarchitectural pipelining. A: IEEE/ACM International Conference on Computer-Aided Design. "2008 IEEE/ACM International Conference on Computer-Aided DesignDigest of Technical Papers". Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 434-441.
dc.identifier.isbn978-1-4244-2819-9
dc.identifier.urihttp://hdl.handle.net/2117/130965
dc.description.abstractThis paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations with a few transformations valid only for elastic systems with early evaluation (namely, empty FIFO insertion, FIFO capacity sizing, insertion of anti-tokens, and introducing early evaluation multiplexors). By converting the design to a synchronous elastic form and then applying this extended set of transformations, one can pipeline a functional specification with an automatically generated distributed controller that implements stalling logic resolving data hazards off the critical path of the design. We have developed an interactive toolkit for exploring elastic microarchitectural transformations. The method is illustrated by pipelining a few simple examples of instruction set architecture ISA specifications.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshLogic circuits
dc.subject.otherMicroarchitecture
dc.subject.otherPipeline processing
dc.subject.otherRadio frequency
dc.subject.otherDelay
dc.subject.otherLogic
dc.subject.otherDistributed control
dc.subject.otherHazards
dc.subject.otherSystolic arrays
dc.subject.otherThroughput
dc.subject.otherSynchronous generators
dc.titleCorrect-by-construction microarchitectural pipelining
dc.typeConference report
dc.subject.lemacCircuits lògics
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/ICCAD.2008.4681612
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/4681612
dc.rights.accessOpen Access
local.identifier.drac2433023
dc.description.versionPostprint (published version)
local.citation.authorKam, T.; Kishinevsky, M.; Cortadella, J.; Galceran, M.
local.citation.contributorIEEE/ACM International Conference on Computer-Aided Design
local.citation.publicationName2008 IEEE/ACM International Conference on Computer-Aided DesignDigest of Technical Papers
local.citation.startingPage434
local.citation.endingPage441


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