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Correct-by-construction microarchitectural pipelining
dc.contributor.author | Kam, Timothy |
dc.contributor.author | Kishinevsky, Michael |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Galcerán Oms, Marc |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2019-03-28T08:14:12Z |
dc.date.available | 2019-03-28T08:14:12Z |
dc.date.issued | 2008 |
dc.identifier.citation | Kam, T. [et al.]. Correct-by-construction microarchitectural pipelining. A: IEEE/ACM International Conference on Computer-Aided Design. "2008 IEEE/ACM International Conference on Computer-Aided DesignDigest of Technical Papers". Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 434-441. |
dc.identifier.isbn | 978-1-4244-2819-9 |
dc.identifier.uri | http://hdl.handle.net/2117/130965 |
dc.description.abstract | This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations with a few transformations valid only for elastic systems with early evaluation (namely, empty FIFO insertion, FIFO capacity sizing, insertion of anti-tokens, and introducing early evaluation multiplexors). By converting the design to a synchronous elastic form and then applying this extended set of transformations, one can pipeline a functional specification with an automatically generated distributed controller that implements stalling logic resolving data hazards off the critical path of the design. We have developed an interactive toolkit for exploring elastic microarchitectural transformations. The method is illustrated by pipelining a few simple examples of instruction set architecture ISA specifications. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Logic circuits |
dc.subject.other | Microarchitecture |
dc.subject.other | Pipeline processing |
dc.subject.other | Radio frequency |
dc.subject.other | Delay |
dc.subject.other | Logic |
dc.subject.other | Distributed control |
dc.subject.other | Hazards |
dc.subject.other | Systolic arrays |
dc.subject.other | Throughput |
dc.subject.other | Synchronous generators |
dc.title | Correct-by-construction microarchitectural pipelining |
dc.type | Conference report |
dc.subject.lemac | Circuits lògics |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ICCAD.2008.4681612 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/4681612 |
dc.rights.access | Open Access |
local.identifier.drac | 2433023 |
dc.description.version | Postprint (published version) |
local.citation.author | Kam, T.; Kishinevsky, M.; Cortadella, J.; Galceran, M. |
local.citation.contributor | IEEE/ACM International Conference on Computer-Aided Design |
local.citation.publicationName | 2008 IEEE/ACM International Conference on Computer-Aided DesignDigest of Technical Papers |
local.citation.startingPage | 434 |
local.citation.endingPage | 441 |