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dc.contributor.authorBlunno, Ivan
dc.contributor.authorCortadella, Jordi
dc.contributor.authorKondratyev, Alex
dc.contributor.authorLavagno, Luciano
dc.contributor.authorLwin, Kelvin
dc.contributor.authorSotiriou, Christos P.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-03-26T10:22:08Z
dc.date.available2019-03-26T10:22:08Z
dc.date.issued2004
dc.identifier.citationBlunno, I. [et al.]. Handshake protocols for de-synchronization. A: IEEE International Symposium on Asynchronous Circuits and Systems. "10th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2004: 19-23 April 2004, Crete, Greece". Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 149-158.
dc.identifier.isbn0-7695-2133-9
dc.identifier.urihttp://hdl.handle.net/2117/130845
dc.description.abstractDe-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronization and formally proves their correctness. Taxonomy of existing protocols for latch controllers is provided. In particular, four-phase handshake protocols devised for micro-pipelines are studied. A new controller with maximum concurrency for de-synchronization is also proposed. The applicability of de-synchronization on an implementation of the DLX microprocessor is also described and discussed.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.lcshMicroprocessors
dc.subject.otherProtocols
dc.subject.otherAutomatic control
dc.subject.otherCircuit synthesis
dc.subject.otherSynchronization
dc.subject.otherClocks
dc.subject.otherNetwork synthesis
dc.subject.otherDesign automation
dc.subject.otherPipelines
dc.titleHandshake protocols for de-synchronization
dc.typeConference report
dc.subject.lemacCircuits asíncrons
dc.subject.lemacMicroprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/ASYNC.2004.1299296
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/1299296
dc.rights.accessOpen Access
local.identifier.drac2451985
dc.description.versionPostprint (published version)
local.citation.authorBlunno, I.; Cortadella, J.; Kondratyev, A.; Lavagno, L.; Lwin, K.; Sotiriou, C. P.
local.citation.contributorIEEE International Symposium on Asynchronous Circuits and Systems
local.citation.publicationName10th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2004: 19-23 April 2004, Crete, Greece
local.citation.startingPage149
local.citation.endingPage158


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