A radix-16 SRT division unit with speculation of the quotient digits
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for standard SRT division and permits us to implement division schemes where a simpler function speculates the quotient digit. This leads to division units with shorter cycle time and variable latency since a speculation error may be produced and a post-correction of the quotient may be necessary. We have applied our algorithm to the design of a radix-16 speculative divider for double precision floating point numbers, that resulted in being faster than analogous implementations.
CitationGianluca, C.; Cortadella, J. A radix-16 SRT division unit with speculation of the quotient digits. A: Great Lakes Symposium on VLSI. "Ninth Great Lakes Symposium on VLSI: Ypsilanti Marriott at Eagle Court, Ypsilanti, Michigan, March 4-6, 1999: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 74-77.
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