Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
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Cita com:
hdl:2117/130421
Tipus de documentText en actes de congrés
Data publicació1999
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions in the form "event a occurs before event b" can be used to remove redundant handshakes and associated logic. This paper presents a method for automatic generation of relative timing assumptions from the untimed specification. These assumptions can be used for area and delay optimization of the circuit. A set of relative timing constraints sufficient for the correct operation of the circuit is back-annotated to the designer. Experimental results for control circuits of a prototype iA32 instruction length decoding and steering unit called RAPPID (Revolving Asynchronous Pentium(R)Processor Instruction Decoder) shows significant improvements in area and delay over speed-independent circuits.
CitacióCortadella, J. [et al.]. Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. A: IEEE/ACM International Conference on Computer-Aided Design. "1999 IEEE/ACM International Conference on Computer-Aided Design: November 7-11, 1999, San Jose, California: digest of technical papers". Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 324-331.
ISBN0-7803-5832-5
Versió de l'editorhttps://ieeexplore.ieee.org/document/810669
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