What is the cost of delay insensitivity?
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Cita com:
hdl:2117/130419
Tipus de documentText en actes de congrés
Data publicació1999
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which the Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.
CitacióSaito, H. [et al.]. What is the cost of delay insensitivity?. A: IEEE/ACM International Conference on Computer-Aided Design. "1999 IEEE/ACM International Conference on Computer-Aided Design: November 7-11, 1999, San Jose, California: digest of technical papers". Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 316-323.
ISBN0-7803-5832-5
Versió de l'editorhttps://ieeexplore.ieee.org/document/810668
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