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dc.contributor.authorStevens, Kenneth S.
dc.contributor.authorRotem, Shai
dc.contributor.authorBurns, Steven M.
dc.contributor.authorCortadella, Jordi
dc.contributor.authorGinosar, Ran
dc.contributor.authorKishinevsky, Michael
dc.contributor.authorRoncken, Marly
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-03-14T07:16:13Z
dc.date.available2019-03-14T07:16:13Z
dc.date.issued1999
dc.identifier.citationStevens, K. [et al.]. CAD directions for high performance asynchronous circuits. A: Design Automation Conference. "36th Design Automation Conference: Ernest N. Morial Convention Center, New Orleans, LA, June 21-25, 1999: proceedings". New York: Association for Computing Machinery (ACM), 1999, p. 116-121.
dc.identifier.isbn1-58113-092-9
dc.identifier.urihttp://hdl.handle.net/2117/130416
dc.description.abstractThis paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 instruction length decoding and steering unit called RAPPID ("revolving asynchronous Pentium processor instruction decoder") that was fabricated and tested successfully. Silicon results show significant advantages-in particular, performance of 2.5-4.5 instructions per nS-with manageable risks using this design technology. RAPPID achieves three times faster performance and half the latency dissipating only half the power and requiring a minor area penalty as a comparable 400 MHz clocked circuit. Relative timing is based on user-defined and automatically extracted relative timing assumptions between signal transitions in a circuit and its environment. It supports the specification, synthesis, and verification of high-performance asynchronous circuits, such as pulse-mode circuits, that can be derived from an initial speed-independent specification. Relative Timing presents a "middle-ground" between clocked and asynchronous circuits, and is a fertile area for CAD development. We discuss possible directions for future CAD development.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshElectronic circuits -- Testing
dc.subject.lcshAsynchronous circuits
dc.subject.lcshElectronic circuit design
dc.subject.otherTiming
dc.subject.otherDesign automation
dc.subject.otherCircuit synthesis
dc.subject.otherDecoding
dc.subject.otherClocks
dc.subject.otherPrototypes
dc.subject.otherCircuit testing
dc.subject.otherSilicon
dc.subject.otherRisk management
dc.titleCAD directions for high performance asynchronous circuits
dc.typeConference report
dc.subject.lemacCircuits electrònics -- Proves
dc.subject.lemacCircuits asíncrons
dc.subject.lemacCircuits electrònics -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1145/309847.309893
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://dl.acm.org/citation.cfm?id=309893
dc.rights.accessOpen Access
local.identifier.drac2432965
dc.description.versionPostprint (author's final draft)
local.citation.authorStevens, K.; Rotem, S.; Burns, S.; Cortadella, J.; Ginosar, R.; Kishinevsky, M.; Roncken, M.
local.citation.contributorDesign Automation Conference
local.citation.pubplaceNew York
local.citation.publicationName36th Design Automation Conference: Ernest N. Morial Convention Center, New Orleans, LA, June 21-25, 1999: proceedings
local.citation.startingPage116
local.citation.endingPage121


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