CAD directions for high performance asynchronous circuits
Document typeConference report
PublisherAssociation for Computing Machinery (ACM)
Rights accessOpen Access
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 instruction length decoding and steering unit called RAPPID ("revolving asynchronous Pentium processor instruction decoder") that was fabricated and tested successfully. Silicon results show significant advantages-in particular, performance of 2.5-4.5 instructions per nS-with manageable risks using this design technology. RAPPID achieves three times faster performance and half the latency dissipating only half the power and requiring a minor area penalty as a comparable 400 MHz clocked circuit. Relative timing is based on user-defined and automatically extracted relative timing assumptions between signal transitions in a circuit and its environment. It supports the specification, synthesis, and verification of high-performance asynchronous circuits, such as pulse-mode circuits, that can be derived from an initial speed-independent specification. Relative Timing presents a "middle-ground" between clocked and asynchronous circuits, and is a fertile area for CAD development. We discuss possible directions for future CAD development.
CitationStevens, K. [et al.]. CAD directions for high performance asynchronous circuits. A: Design Automation Conference. "36th Design Automation Conference: Ernest N. Morial Convention Center, New Orleans, LA, June 21-25, 1999: proceedings". New York: Association for Computing Machinery (ACM), 1999, p. 116-121.
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