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dc.contributor.authorRoig Mansilla, Oriol
dc.contributor.authorCortadella, Jordi
dc.contributor.authorPeña Basurto, Marco Antonio
dc.contributor.authorPastor Llorens, Enric
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-03-12T09:45:43Z
dc.date.available2019-03-12T09:45:43Z
dc.date.issued1997
dc.identifier.citationRoig, O. [et al.]. Automatic generation of synchronous test patterns for asynchronous circuits. A: Design Automation Conference. "Design Automation Conference, 34th DAC: Anaheim, CA, Anaheim Convention Center, June 9-13,1997: proceedings 1997". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 620-625.
dc.identifier.isbn0-7803-4093-0
dc.identifier.urihttp://hdl.handle.net/2117/130226
dc.description.abstractThis paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, as is done by real-life testers. The main contribution of the paper is the abstraction of the circuit’s behavior as a synchronous finite state machine in such a way that similar techniques to those currently used for synchronous circuits can be safely applied for testing. Currently, the fault model being used is the input stuck-at model. Experimental results on different benchmarks show that our approach generates test vectors with high fault coverage.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.otherCircuit testing
dc.subject.otherAutomatic test pattern generation
dc.subject.otherSynchronous generators
dc.subject.otherTest pattern generators
dc.subject.otherAutomatic testing
dc.subject.otherCircuit faults
dc.subject.otherDelay
dc.subject.otherDesign for testability
dc.subject.otherPermission
dc.titleAutomatic generation of synchronous test patterns for asynchronous circuits
dc.typeConference report
dc.subject.lemacCircuits asíncrons
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/DAC.1997.597220
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/597220
dc.rights.accessOpen Access
local.identifier.drac2375895
dc.description.versionPostprint (published version)
local.citation.authorRoig, O.; Cortadella, J.; Peña, M.; Pastor, E.
local.citation.contributorDesign Automation Conference
local.citation.publicationNameDesign Automation Conference, 34th DAC: Anaheim, CA, Anaheim Convention Center, June 9-13,1997: proceedings 1997
local.citation.startingPage620
local.citation.endingPage625


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