On the variability-aware design of memristor-based logic circuits
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Ever since the advent of the first TiO 2 -based memristor and the respective linear model published by Hewlett-Packard Labs, several behavioral models of memristors have been published. Such models capture the fundamental characteristics of resistive switching behavior through simple equations and rules, so they received a lot of attention and contributed significantly to the fast progress of research in this new and emerging device technology field. However, while this technology is maturing, accurate physics-based models are being developed, which go deeper into the device dynamics and capture more details than what just would be the fundamentals: i.e. parasitics of the device structure, variability of threshold voltages and resistance states, temperature dependency, dynamic current fluctuations, etc. In this work we build upon such a physics-based model of a bipolar metal-oxide resistive RAM device, showing how to take into account device variability and its significance in evaluation of processing circuits. With the Cadence Virtuoso suite, we focus on a family of memristive logic gate implementations showing that read & write errors can emerge due to both variability and state-drift impact, features rarely seen so far in results shown in other relevant published works.
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CitationEscudero, M. [et al.]. On the variability-aware design of memristor-based logic circuits. A: IEEE International Conference on Nanotechnology. "18th International Conference on Nanotechnology (IEEE-NANO): Cork, Ireland: 23-26 July 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-4.