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dc.contributor.authorMonchiero, Matteo
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2011-07-20T09:46:51Z
dc.date.available2011-07-20T09:46:51Z
dc.date.created2009
dc.date.issued2009
dc.identifier.citationMonchiero, M.; Canal, R.; González, A. Using coherence information and decay techniques to optimize L2 cache leakage in CMPs. A: International Conference on Parallel Processing. "38th International Conference on Parallel Processing". Viena: IEEE Computer Society, 2009, p. 1-8.
dc.identifier.isbn978-0-7695-3802-0
dc.identifier.urihttp://hdl.handle.net/2117/13014
dc.description.abstractThis paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches. Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21% energy reduction, respectively, at the cost of 0%, 8%, and 2% performance loss. For other cache sizes the behavior is qualitatively similar.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherIEEE Computer Society
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.otherLeakage
dc.subject.otherChip multiprocessor
dc.subject.otherCMP
dc.subject.otherMulticore
dc.subject.otherCache decay
dc.subject.otherCoherence
dc.titleUsing coherence information and decay techniques to optimize L2 cache leakage in CMPs
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/ICPP.2009.28
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://portal.acm.org/citation.cfm?id=1679670
dc.rights.accessOpen Access
local.identifier.drac2473213
dc.description.versionPostprint (published version)
local.citation.authorMonchiero, M.; Canal, R.; González, A.
local.citation.contributorInternational Conference on Parallel Processing
local.citation.pubplaceViena
local.citation.publicationName38th International Conference on Parallel Processing
local.citation.startingPage1
local.citation.endingPage8


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