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Variability-tolerant memristor-based ratioed logic in crossbar array
dc.contributor.author | Escudero López, Manuel |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Vourkas, Ioannis |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2019-03-07T14:04:28Z |
dc.date.available | 2019-03-07T14:04:28Z |
dc.date.issued | 2018 |
dc.identifier.citation | Escudero, M. [et al.]. Variability-tolerant memristor-based ratioed logic in crossbar array. A: IEEE/ACM International Symposium on Nanoscale Architectures. "2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-6. |
dc.identifier.isbn | 9781538662939 |
dc.identifier.uri | http://hdl.handle.net/2117/130146 |
dc.description | The final publication is available at ACM via http://dx.doi.org/10.1145/3232195.3232213 |
dc.description.abstract | The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this de- vice technology, with several emerging applications including that of logic circuits. Several memristive logic families have been pro- posed, each with different attributes, in the current quest for energy- efficient computing systems of the future. However, limited en- durance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and va- riability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Àrees temàtiques de la UPC::Enginyeria elèctrica |
dc.subject.lcsh | Computer architecture |
dc.subject.other | Ratioed logic gates |
dc.subject.other | crossbar |
dc.subject.other | memristor |
dc.subject.other | logic design |
dc.subject.other | variability- aware design. |
dc.title | Variability-tolerant memristor-based ratioed logic in crossbar array |
dc.type | Conference report |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1145/3232195.3232213 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8604365 |
dc.rights.access | Open Access |
local.identifier.drac | 23955081 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO/1PE/TEC2016-75151-C3-2-R |
local.citation.author | Escudero, M.; Rubio, A.; Moll, F.; Vourkas, I. |
local.citation.contributor | IEEE/ACM International Symposium on Nanoscale Architectures |
local.citation.publicationName | 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018 |
local.citation.startingPage | 1 |
local.citation.endingPage | 6 |