Variability-tolerant memristor-based ratioed logic in crossbar array
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this de- vice technology, with several emerging applications including that of logic circuits. Several memristive logic families have been pro- posed, each with different attributes, in the current quest for energy- efficient computing systems of the future. However, limited en- durance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and va- riability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.
The final publication is available at ACM via http://dx.doi.org/10.1145/3232195.3232213
CitationEscudero, M. [et al.]. Variability-tolerant memristor-based ratioed logic in crossbar array. A: IEEE/ACM International Symposium on Nanoscale Architectures. "2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-6.
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