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dc.contributor.authorRallis, Konstantinos
dc.contributor.authorSirakoulis, Georgios
dc.contributor.authorKarafyllidis, Ioannis
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2019-03-07T13:56:53Z
dc.date.available2019-03-07T13:56:53Z
dc.date.issued2018
dc.identifier.citationRallis, K. [et al.]. Multi-valued logic circuits on graphene quantum point contact devices. A: IEEE/ACM International Symposium on Nanoscale Architectures. "2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-5.
dc.identifier.isbn9781538662939
dc.identifier.urihttp://hdl.handle.net/2117/130144
dc.descriptionThe final publication is available at ACM via http://dx.doi.org/10.1145/3232195.3232214
dc.description.abstractGraphene quantum point contacts (G-QPC) combine switching operations with quantized conductance, which can be modulated by top and back gates. Here we use the conductance quantization to design and simulate multi-valued logic (MVL) circuits and, more specifically an adder. The adder comprises two G-QPCs connected in parallel. We compute the conductance of the adder for various inputs and show that Graphene MVL circuits are feasible.
dc.format.extent5 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer architecture
dc.subject.otherGraphene
dc.subject.otherGraphene Quantum Point Contact
dc.subject.otherMulti-Valued Logic
dc.subject.otherAdder
dc.titleMulti-valued logic circuits on graphene quantum point contact devices
dc.typeConference report
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1145/3232195.3232214
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8604348
dc.rights.accessOpen Access
local.identifier.drac23955044
dc.description.versionPostprint (author's final draft)
local.citation.authorRallis, K.; Sirakoulis, G.; Karafyllidis, I.; Rubio, A.
local.citation.contributorIEEE/ACM International Symposium on Nanoscale Architectures
local.citation.publicationName2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018
local.citation.startingPage1
local.citation.endingPage5


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