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Multi-valued logic circuits on graphene quantum point contact devices
dc.contributor.author | Rallis, Konstantinos |
dc.contributor.author | Sirakoulis, Georgios |
dc.contributor.author | Karafyllidis, Ioannis |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2019-03-07T13:56:53Z |
dc.date.available | 2019-03-07T13:56:53Z |
dc.date.issued | 2018 |
dc.identifier.citation | Rallis, K. [et al.]. Multi-valued logic circuits on graphene quantum point contact devices. A: IEEE/ACM International Symposium on Nanoscale Architectures. "2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-5. |
dc.identifier.isbn | 9781538662939 |
dc.identifier.uri | http://hdl.handle.net/2117/130144 |
dc.description | The final publication is available at ACM via http://dx.doi.org/10.1145/3232195.3232214 |
dc.description.abstract | Graphene quantum point contacts (G-QPC) combine switching operations with quantized conductance, which can be modulated by top and back gates. Here we use the conductance quantization to design and simulate multi-valued logic (MVL) circuits and, more specifically an adder. The adder comprises two G-QPCs connected in parallel. We compute the conductance of the adder for various inputs and show that Graphene MVL circuits are feasible. |
dc.format.extent | 5 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Computer architecture |
dc.subject.other | Graphene |
dc.subject.other | Graphene Quantum Point Contact |
dc.subject.other | Multi-Valued Logic |
dc.subject.other | Adder |
dc.title | Multi-valued logic circuits on graphene quantum point contact devices |
dc.type | Conference report |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1145/3232195.3232214 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8604348 |
dc.rights.access | Open Access |
local.identifier.drac | 23955044 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Rallis, K.; Sirakoulis, G.; Karafyllidis, I.; Rubio, A. |
local.citation.contributor | IEEE/ACM International Symposium on Nanoscale Architectures |
local.citation.publicationName | 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2018): Athens, Greece: 17-19 July 2018 |
local.citation.startingPage | 1 |
local.citation.endingPage | 5 |