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dc.contributor.authorCortadella, Jordi
dc.contributor.authorKishinevsky, Michael
dc.contributor.authorKondratyev, Alex
dc.contributor.authorLavagno, Luciano
dc.contributor.authorPastor Llorens, Enric
dc.contributor.authorYakovlev, Alex
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-03-07T10:56:25Z
dc.date.available2019-03-07T10:56:25Z
dc.date.issued1997
dc.identifier.citationCortadella, J. [et al.]. Decomposition and technology mapping of speed-independent circuits using Boolean relations. A: IEEE/ACM International Conference on Computer-Aided Design. "1997 IEEE/ACM International Conference on Computer-Aided Design: November 9-13, 1997 San Jose, California". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 220-227.
dc.identifier.isbn0-8186-8200-0
dc.identifier.urihttp://hdl.handle.net/2117/130128
dc.description.abstractPresents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G, which is available in the library, and two gates H/sub 1/ and H/sub 2/, which are simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H/sub 1/ and H/sub 2/, the method uses Boolean relations, as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H/sub 1/ and H/sub 2/, allows for the sharing of decomposed logic. Overall, this method is more general than existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.lcshLogic circuits
dc.subject.lcshLogic design
dc.subject.otherCircuit CAD
dc.subject.otherLogic gates
dc.subject.otherBoolean algebra
dc.subject.otherLogic CAD
dc.subject.otherLogic partitioning
dc.titleDecomposition and technology mapping of speed-independent circuits using Boolean relations
dc.typeConference report
dc.subject.lemacCircuits asíncrons
dc.subject.lemacCircuits lògics
dc.subject.lemacEstructura lògica
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ICCAD.1997.643524
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore-ieee-org.recursos.biblioteca.upc.edu/document/643524
dc.rights.accessOpen Access
drac.iddocument2338195
dc.description.versionPostprint (published version)
upcommons.citation.authorCortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Pastor, E.; Yakovlev, A.
upcommons.citation.contributorIEEE/ACM International Conference on Computer-Aided Design
upcommons.citation.publishedtrue
upcommons.citation.publicationName1997 IEEE/ACM International Conference on Computer-Aided Design: November 9-13, 1997 San Jose, California
upcommons.citation.startingPage220
upcommons.citation.endingPage227


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