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Decomposition and technology mapping of speed-independent circuits using Boolean relations
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Kishinevsky, Michael |
dc.contributor.author | Kondratyev, Alex |
dc.contributor.author | Lavagno, Luciano |
dc.contributor.author | Pastor Llorens, Enric |
dc.contributor.author | Yakovlev, Alex |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2019-03-07T10:56:25Z |
dc.date.available | 2019-03-07T10:56:25Z |
dc.date.issued | 1997 |
dc.identifier.citation | Cortadella, J. [et al.]. Decomposition and technology mapping of speed-independent circuits using Boolean relations. A: IEEE/ACM International Conference on Computer-Aided Design. "1997 IEEE/ACM International Conference on Computer-Aided Design: November 9-13, 1997 San Jose, California". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 220-227. |
dc.identifier.isbn | 0-8186-8200-0 |
dc.identifier.uri | http://hdl.handle.net/2117/130128 |
dc.description.abstract | Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed method iteratively performs Boolean decomposition of each such gate F into a two-input combinational or sequential gate G, which is available in the library, and two gates H/sub 1/ and H/sub 2/, which are simpler than F, while preserving the original behavior and speed-independence of the circuit. To extract functions for H/sub 1/ and H/sub 2/, the method uses Boolean relations, as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, overall library matching and optimization is carried out. Logic resynthesis, performed after speed-independent signal insertion for H/sub 1/ and H/sub 2/, allows for the sharing of decomposed logic. Overall, this method is more general than existing techniques based on restricted decomposition architectures, and thereby leads to better results in technology mapping. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Asynchronous circuits |
dc.subject.lcsh | Logic circuits |
dc.subject.lcsh | Logic design |
dc.subject.other | Circuit CAD |
dc.subject.other | Logic gates |
dc.subject.other | Boolean algebra |
dc.subject.other | Logic CAD |
dc.subject.other | Logic partitioning |
dc.title | Decomposition and technology mapping of speed-independent circuits using Boolean relations |
dc.type | Conference report |
dc.subject.lemac | Circuits asíncrons |
dc.subject.lemac | Circuits lògics |
dc.subject.lemac | Estructura lògica |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/ICCAD.1997.643524 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore-ieee-org.recursos.biblioteca.upc.edu/document/643524 |
dc.rights.access | Open Access |
local.identifier.drac | 2338195 |
dc.description.version | Postprint (published version) |
local.citation.author | Cortadella, J.; Kishinevsky, M.; Kondratyev, A.; Lavagno, L.; Pastor, E.; Yakovlev, A. |
local.citation.contributor | IEEE/ACM International Conference on Computer-Aided Design |
local.citation.publicationName | 1997 IEEE/ACM International Conference on Computer-Aided Design: November 9-13, 1997 San Jose, California |
local.citation.startingPage | 220 |
local.citation.endingPage | 227 |