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dc.contributor.authorBenedicte Illescas, Pedro
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorMezzetti, Enrico
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.authorHernández Luz, Carles
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Enginyeria Telemàtica
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2019-03-06T17:55:53Z
dc.date.issued2019
dc.identifier.citationBenedicte, P. [et al.]. Towards limiting the impact of timing anomalies in complex real-time processors. A: Asia and South Pacific Design Automation Conference. "ASPDAC '19: proceedings of the 24th Asia and South Pacific Design Automation Conference", 21 Gener 2019, p. 27-32.
dc.identifier.isbn978-1-4503-6007-4
dc.identifier.urihttp://hdl.handle.net/2117/130115
dc.description.abstractTiming verification of embedded critical real-time systems is hindered by complex designs. Timing anomalies, deeply analyzed in static timing analysis, require specific solutions to bound their impact. For the first time, we study the concept and impact of timing anomalies in measurement-based timing analysis, the most used in industry, showing that they require to be considered and handled differently. In addition, we analyze anomalies in the context of Measurement-Based Probabilistic Timing Analysis, which simplifies quantifying their impact.
dc.format.extent6 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits
dc.subject.otherEmbedded critical systems
dc.subject.otherTiming Ananomalies
dc.subject.otherWCET Computer aided design
dc.subject.otherEmbedded systems
dc.subject.otherInteractive computer systems
dc.subject.otherTiming circuits
dc.subject.otherCritical systems
dc.subject.otherMeasurement-based
dc.subject.otherReal time processors
dc.subject.otherStatic timing analysis
dc.subject.otherTiming Ananomalies
dc.subject.otherTiming anomalies
dc.subject.otherTiming verification
dc.subject.otherWCET
dc.subject.otherReal time systems
dc.titleTowards limiting the impact of timing anomalies in complex real-time processors
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.identifier.doi10.1145/3287624.3287655
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://dl.acm.org/citation.cfm?id=3287655
dc.rights.accessOpen Access
local.identifier.drac23956199
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom
dc.date.lift10000-01-01
local.citation.authorBenedicte, P.; Abella, J.; Hernández, C.; Mezzetti, E.; Cazorla, F. J.
local.citation.contributorAsia and South Pacific Design Automation Conference
local.citation.publicationNameASPDAC '19: proceedings of the 24th Asia and South Pacific Design Automation Conference
local.citation.startingPage27
local.citation.endingPage32


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