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Towards limiting the impact of timing anomalies in complex real-time processors
dc.contributor.author | Benedicte Illescas, Pedro |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Mezzetti, Enrico |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Hernández Luz, Carles |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Doctorat en Enginyeria Telemàtica |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2019-03-06T17:55:53Z |
dc.date.issued | 2019 |
dc.identifier.citation | Benedicte, P. [et al.]. Towards limiting the impact of timing anomalies in complex real-time processors. A: Asia and South Pacific Design Automation Conference. "ASPDAC '19: proceedings of the 24th Asia and South Pacific Design Automation Conference", 21 Gener 2019, p. 27-32. |
dc.identifier.isbn | 978-1-4503-6007-4 |
dc.identifier.uri | http://hdl.handle.net/2117/130115 |
dc.description.abstract | Timing verification of embedded critical real-time systems is hindered by complex designs. Timing anomalies, deeply analyzed in static timing analysis, require specific solutions to bound their impact. For the first time, we study the concept and impact of timing anomalies in measurement-based timing analysis, the most used in industry, showing that they require to be considered and handled differently. In addition, we analyze anomalies in the context of Measurement-Based Probabilistic Timing Analysis, which simplifies quantifying their impact. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits |
dc.subject.other | Embedded critical systems |
dc.subject.other | Timing Ananomalies |
dc.subject.other | WCET Computer aided design |
dc.subject.other | Embedded systems |
dc.subject.other | Interactive computer systems |
dc.subject.other | Timing circuits |
dc.subject.other | Critical systems |
dc.subject.other | Measurement-based |
dc.subject.other | Real time processors |
dc.subject.other | Static timing analysis |
dc.subject.other | Timing Ananomalies |
dc.subject.other | Timing anomalies |
dc.subject.other | Timing verification |
dc.subject.other | WCET |
dc.subject.other | Real time systems |
dc.title | Towards limiting the impact of timing anomalies in complex real-time processors |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats |
dc.identifier.doi | 10.1145/3287624.3287655 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://dl.acm.org/citation.cfm?id=3287655 |
dc.rights.access | Open Access |
local.identifier.drac | 23956199 |
dc.description.version | Postprint (published version) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom |
dc.date.lift | 10000-01-01 |
local.citation.author | Benedicte, P.; Abella, J.; Hernández, C.; Mezzetti, E.; Cazorla, F. J. |
local.citation.contributor | Asia and South Pacific Design Automation Conference |
local.citation.publicationName | ASPDAC '19: proceedings of the 24th Asia and South Pacific Design Automation Conference |
local.citation.startingPage | 27 |
local.citation.endingPage | 32 |