Mostra el registre d'ítem simple
Individual flip-flops with gated clocks for low power datapaths
dc.contributor.author | Lang, Tomás |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Musoll Cinca, Enric |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2019-02-21T12:33:07Z |
dc.date.available | 2019-02-21T12:33:07Z |
dc.date.issued | 1997-06 |
dc.identifier.citation | Lang, T.; Cortadella, J.; Musoll, E. Individual flip-flops with gated clocks for low power datapaths. "IEEE transactions on circuits and systems II: analog and digital signal processing", Juny 1997, vol. 44, núm. 6, p. 507-516. |
dc.identifier.issn | 1057-7130 |
dc.identifier.uri | http://hdl.handle.net/2117/129522 |
dc.description.abstract | Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Logic circuits |
dc.subject.lcsh | Microprocessors -- Energy consumption |
dc.subject.other | Flip-flops |
dc.subject.other | Clocks |
dc.subject.other | Energy consumption |
dc.subject.other | CMOS technology |
dc.subject.other | Digital systems |
dc.subject.other | Batteries |
dc.subject.other | Wireless communication |
dc.subject.other | Power system modeling |
dc.subject.other | Circuit simulation |
dc.subject.other | Registers |
dc.title | Individual flip-flops with gated clocks for low power datapaths |
dc.type | Article |
dc.subject.lemac | Circuits lògics |
dc.subject.lemac | Microprocessadors -- Consum d'energia |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/82.592586 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/592586 |
dc.rights.access | Open Access |
local.identifier.drac | 1636404 |
dc.description.version | Postprint (published version) |
local.citation.author | Lang, T.; Cortadella, J.; Musoll, E. |
local.citation.publicationName | IEEE transactions on circuits and systems II: analog and digital signal processing |
local.citation.volume | 44 |
local.citation.number | 6 |
local.citation.startingPage | 507 |
local.citation.endingPage | 516 |
Fitxers d'aquest items
Aquest ítem apareix a les col·leccions següents
-
Articles de revista [1.049]
-
Articles de revista [274]