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dc.contributor.authorLang, Tomás
dc.contributor.authorCortadella, Jordi
dc.contributor.authorMusoll Cinca, Enric
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-02-21T12:33:07Z
dc.date.available2019-02-21T12:33:07Z
dc.date.issued1997-06
dc.identifier.citationLang, T.; Cortadella, J.; Musoll, E. Individual flip-flops with gated clocks for low power datapaths. "IEEE transactions on circuits and systems II: analog and digital signal processing", Juny 1997, vol. 44, núm. 6, p. 507-516.
dc.identifier.issn1057-7130
dc.identifier.urihttp://hdl.handle.net/2117/129522
dc.description.abstractEnergy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices with wireless communication capabilities. Flip-flops are one of the most energy-consuming components of digital circuits. This paper presents techniques to reduce energy consumption by individually deactivating the clock when flip-flops do not have to change their value. Flip-flop structures are proposed and selection criteria given to obtain minimum energy consumption. The structures have been evaluated using energy models and validated by switch-level simulations. For the applications considered, significant energy reductions are achieved.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshLogic circuits
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.otherFlip-flops
dc.subject.otherClocks
dc.subject.otherEnergy consumption
dc.subject.otherCMOS technology
dc.subject.otherDigital systems
dc.subject.otherBatteries
dc.subject.otherWireless communication
dc.subject.otherPower system modeling
dc.subject.otherCircuit simulation
dc.subject.otherRegisters
dc.titleIndividual flip-flops with gated clocks for low power datapaths
dc.typeArticle
dc.subject.lemacCircuits lògics
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/82.592586
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/592586
dc.rights.accessOpen Access
drac.iddocument1636404
dc.description.versionPostprint (published version)
upcommons.citation.authorLang, T.; Cortadella, J.; Musoll, E.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on circuits and systems II: analog and digital signal processing
upcommons.citation.volume44
upcommons.citation.number6
upcommons.citation.startingPage507
upcommons.citation.endingPage516


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