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dc.contributor.authorPastor Llorens, Enric
dc.contributor.authorCortadella, Jordi
dc.contributor.authorKondratyev, Alex
dc.contributor.authorRoig Mansilla, Oriol
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-02-21T10:39:06Z
dc.date.available2019-02-21T10:39:06Z
dc.date.issued1996
dc.identifier.citationPastor, E. [et al.]. Structural methods for the synthesis of speed-independent circuits. A: European Design and Test Conference. "European Design & Test Conference, ED&TC 96: March 11-14, 1996, Paris, France: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1996, p. 340-347.
dc.identifier.isbn0-8186-7424-5
dc.identifier.urihttp://hdl.handle.net/2117/129510
dc.description.abstractMost existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based on the structural analysis of the underlying Petri net. This methodology can be applied to any STG that can be covered by State Machines and, in particular to all live and safe free-choice STGs. Significant improvements with regard to existing structural methods are provided. The new techniques have been implemented in an experimental tool that has been able to synthesize specifications with over 10/sup 27/ markings, some of them being non-free choice.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.lcshLogic design
dc.subject.lcshPetri nets
dc.subject.otherNetwork synthesis
dc.subject.otherSignal flow graphs
dc.titleStructural methods for the synthesis of speed-independent circuits
dc.typeConference report
dc.subject.lemacCircuits asíncrons
dc.subject.lemacEstructura lògica
dc.subject.lemacPetri, Xarxes de
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/EDTC.1996.494323
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/494323
dc.rights.accessOpen Access
local.identifier.drac2471663
dc.description.versionPostprint (published version)
local.citation.authorPastor, E.; Cortadella, J.; Kondratyev, A.; Roig, O.
local.citation.contributorEuropean Design and Test Conference
local.citation.publicationNameEuropean Design & Test Conference, ED&TC 96: March 11-14, 1996, Paris, France: proceedings
local.citation.startingPage340
local.citation.endingPage347


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