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dc.contributor.authorKondratyev, Alex
dc.contributor.authorCortadella, Jordi
dc.contributor.authorKishinevsky, Michael
dc.contributor.authorPastor Llorens, Enric
dc.contributor.authorRoig Mansilla, Oriol
dc.contributor.authorYakovlev, Alex
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-02-14T09:41:15Z
dc.date.available2019-02-14T09:41:15Z
dc.date.issued1995
dc.identifier.citationKondratyev, A. [et al.]. Checking signal transition graph implementability by symbolic bdd traversal. A: European Design and Automation Conference. "Proceedings the European Design and Test Conference, ED&TC 1995". Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 325-332.
dc.identifier.isbn0-8186-7039-8
dc.identifier.urihttp://hdl.handle.net/2117/129092
dc.description.abstractThis paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification under the restricted input-output interface between the design and the environment, i.e., when no additional interface signals are allowed to be added to the design. We develop algorithms and present experimental results of using BDD-traversal for checking STG implementability. These results demonstrate efficiency of the symbolic approach and show a way of improving existing tools for STG-based asynchronous circuit design.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.lcshLogic design
dc.subject.lcshElectronic circuit design
dc.subject.otherSignal flow graphs
dc.subject.otherSequential circuits
dc.subject.otherLogic CAD
dc.subject.otherCircuit CAD
dc.titleChecking signal transition graph implementability by symbolic bdd traversal
dc.typeConference report
dc.subject.lemacCircuits asíncrons
dc.subject.lemacEstructura lògica
dc.subject.lemacCircuits electrònics -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/EDTC.1995.470376
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/470376
dc.rights.accessOpen Access
local.identifier.drac2377005
dc.description.versionPostprint (published version)
local.citation.authorKondratyev, A.; Cortadella, J.; Kishinevsky, M.; Pastor, E.; Roig, O.; Yakovlev, A.
local.citation.contributorEuropean Design and Automation Conference
local.citation.publicationNameProceedings the European Design and Test Conference, ED&TC 1995
local.citation.startingPage325
local.citation.endingPage332


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