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A new look at the conditions for the synthesis of speed-independent circuits
dc.contributor.author | Pastor Llorens, Enric |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Roig Mansilla, Oriol |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2019-02-14T09:29:35Z |
dc.date.available | 2019-02-14T09:29:35Z |
dc.date.issued | 1995 |
dc.identifier.citation | Pastor, E.; Cortadella, J.; Roig, O. A new look at the conditions for the synthesis of speed-independent circuits. A: Great Lakes Symposium on VLSI. "Fifth Great Lakes Symposium on VLSI: The State University of New York at Buffalo, March 16-18, 1995: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 230-235. |
dc.identifier.isbn | 0-8186-7035-5 |
dc.identifier.uri | http://hdl.handle.net/2117/129085 |
dc.description.abstract | This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures that use simple AND-gates, and do not exploit the advantages offered by the existence of complex gates. The use of complex gates increases the speed and reduces the area of the circuits. These improvements are achieved because of (1) the elimination of the distributivity, signal persistency and unique minimal state requirements imposed by other techniques; (2) the reduction in the number of internal signals necessary to guarantee the synthesis; and finally (3) the utilization of optimization techniques to reduce the fan-in of the involved gates and the number of required memory elements. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits -- Design and construction |
dc.subject.lcsh | Logic design |
dc.subject.lcsh | Logic circuits |
dc.subject.other | Integrated logic circuits |
dc.subject.other | VLSI |
dc.subject.other | Logic CAD |
dc.subject.other | Circuit CAD |
dc.subject.other | Circuit optimisation |
dc.title | A new look at the conditions for the synthesis of speed-independent circuits |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats -- Disseny i construcció |
dc.subject.lemac | Estructura lògica |
dc.subject.lemac | Circuits lògics |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/GLSV.1995.516058 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/516058 |
dc.rights.access | Open Access |
local.identifier.drac | 2472777 |
dc.description.version | Postprint (published version) |
local.citation.author | Pastor, E.; Cortadella, J.; Roig, O. |
local.citation.contributor | Great Lakes Symposium on VLSI |
local.citation.publicationName | Fifth Great Lakes Symposium on VLSI: The State University of New York at Buffalo, March 16-18, 1995: proceedings |
local.citation.startingPage | 230 |
local.citation.endingPage | 235 |