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dc.contributor.authorPastor Llorens, Enric
dc.contributor.authorCortadella, Jordi
dc.contributor.authorRoig Mansilla, Oriol
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-02-14T09:29:35Z
dc.date.available2019-02-14T09:29:35Z
dc.date.issued1995
dc.identifier.citationPastor, E.; Cortadella, J.; Roig, O. A new look at the conditions for the synthesis of speed-independent circuits. A: Great Lakes Symposium on VLSI. "Fifth Great Lakes Symposium on VLSI: The State University of New York at Buffalo, March 16-18, 1995: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 230-235.
dc.identifier.isbn0-8186-7035-5
dc.identifier.urihttp://hdl.handle.net/2117/129085
dc.description.abstractThis paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures that use simple AND-gates, and do not exploit the advantages offered by the existence of complex gates. The use of complex gates increases the speed and reduces the area of the circuits. These improvements are achieved because of (1) the elimination of the distributivity, signal persistency and unique minimal state requirements imposed by other techniques; (2) the reduction in the number of internal signals necessary to guarantee the synthesis; and finally (3) the utilization of optimization techniques to reduce the fan-in of the involved gates and the number of required memory elements.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits -- Design and construction
dc.subject.lcshLogic design
dc.subject.lcshLogic circuits
dc.subject.otherIntegrated logic circuits
dc.subject.otherVLSI
dc.subject.otherLogic CAD
dc.subject.otherCircuit CAD
dc.subject.otherCircuit optimisation
dc.titleA new look at the conditions for the synthesis of speed-independent circuits
dc.typeConference report
dc.subject.lemacCircuits integrats -- Disseny i construcció
dc.subject.lemacEstructura lògica
dc.subject.lemacCircuits lògics
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/GLSV.1995.516058
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/516058
dc.rights.accessOpen Access
local.identifier.drac2472777
dc.description.versionPostprint (published version)
local.citation.authorPastor, E.; Cortadella, J.; Roig, O.
local.citation.contributorGreat Lakes Symposium on VLSI
local.citation.publicationNameFifth Great Lakes Symposium on VLSI: The State University of New York at Buffalo, March 16-18, 1995: proceedings
local.citation.startingPage230
local.citation.endingPage235


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