Division with speculation of quotient digits
Visualitza/Obre
Cita com:
hdl:2117/128608
Tipus de documentText en actes de congrés
Data publicació1993
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selection, so that implementations are limited to low-radix stages. A scheme is presented in which the quotient-digit is speculated and, when this speculation is incorrect, a rollback or a partial advance is performed. This results in a division operation with a shorter cycle time and a variable number of cycles. Several designs have been realized, and a radix-64 implementation that is 30% faster than the fastest conventional implementation (radix-8) at an increase of about 45% in area per quotient bit has been obtained. A radix-16 implementation that is about 10% faster than the radix-8 conventional one, with the additional advantage of requiring about 25% less area per quotient bit, is also shown
CitacióCortadella, J.; Lang, T. Division with speculation of quotient digits. A: IEEE Symposium on Computer Arithmetic. "Proceedings of IEEE 11th Symposium on Computer Arithmetic". Institute of Electrical and Electronics Engineers (IEEE), 1993, p. 87-94.
ISBN0-8186-3862-1
Versió de l'editorhttps://ieeexplore.ieee.org/document/378105
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