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dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorGómez Pau, Álvaro
dc.contributor.authorManich Bou, Salvador
dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorBargalló, Mireia
dc.contributor.authorCampabadal, Francesca
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2019-01-24T12:27:55Z
dc.date.available2019-01-24T12:27:55Z
dc.date.issued2018-12-12
dc.identifier.citationArumi, D. [et al.]. Unpredictable bits generation based on RRAM parallel configuration. "IEEE electron device letters", 12 Desembre 2018, vol. 40, núm. 2, p. 341-344.
dc.identifier.issn0741-3106
dc.identifier.urihttp://hdl.handle.net/2117/127528
dc.description.abstractIn this letter a cell with the parallel combination of two TiN/Ti/HfO2/W resistive random access memory (RRAM) devices is studied for the generation of unpredictable bits. Measurements confirm that a simultaneous parallel SET operation in which one of the two RRAMs switches to the low resistance state (LRS) is an unpredictable process showing random properties for different sets of cells. Furthermore, given a device pair, the same device switches during subsequent write operations. The proposed cell is also analyzed under different current compliances and pulse widths with the same persistent behavior being observed. The features of the proposed cell, which provide data obfuscation without compromising reliability, pave the way for its application in Physical Unclonable Functions (PUFs) for hardware security purposes.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Seguretat informàtica
dc.subject.lcshElectrodes
dc.subject.lcshElectric resistance
dc.subject.lcshComputer security
dc.subject.otherRRAM
dc.subject.othervariability
dc.subject.otherPUF
dc.subject.otherhardware security
dc.titleUnpredictable bits generation based on RRAM parallel configuration
dc.typeArticle
dc.subject.lemacElèctrodes
dc.subject.lemacResistència elèctrica
dc.subject.lemacSeguretat informàtica
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.doi10.1109/LED.2018.2886396
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8573799
dc.rights.accessOpen Access
local.identifier.drac23565247
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TEC2017-84321-C4-1-R/ES/FABRICACION, CARACTERIZACION, SIMULACION, MODELADO Y APLICACIONES DE DISPOSITIVOS DE CONMUTACION RESISTIVA/
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2013-41209-P/ES/ANALISIS Y TECNICAS DE MEJORA DE LA ROBUSTEZ Y SEGURIDAD DE CIRCUITOS NANOMETRICOS EN PRESENCIA DE ATAQUES, DEFECTOS, VARIABILIDAD Y AGING/
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2014-54906-JIN/ES/CARACTERIZACION AVANZADA Y MODELADO DE LA VARIABILIDAD Y FIABILIDAD DE DISPOSITIVOS DE CONMUTACION RESISTIVA PARA APLICACIONES DE MEMORIA NO VOLATIL/
local.citation.authorArumi, D.; Álvaro Gómez-Pau; Manich, S.; Rodriguez-Montanes, R.; Bargalló, M.; Campabadal, F.
local.citation.publicationNameIEEE electron device letters
local.citation.volume40
local.citation.number2
local.citation.startingPage341
local.citation.endingPage344


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