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dc.contributor.authorCortadella, Jordi
dc.contributor.authorKondratyev, Alex
dc.contributor.authorLavagno, Luciano
dc.contributor.authorSotiriou, Christos
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-01-10T07:39:57Z
dc.date.available2019-01-10T07:39:57Z
dc.date.issued2006-10
dc.identifier.citationCortadella, J., Kondratyev, A., Lavagno, L., Sotiriou, C. Desynchronization: Synthesis of asynchronous circuits from synchronous specifications. "IEEE transactions on computer-aided design of integrated circuits and systems", Octubre 2006, vol. 25, núm. 10, p. 1904-1921.
dc.identifier.issn0278-0070
dc.identifier.urihttp://hdl.handle.net/2117/126455
dc.description.abstractAsynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture.
dc.format.extent18 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshAsynchronous circuits
dc.subject.lcshIntegrated circuits -- Design and construction
dc.subject.lcshLogic design
dc.subject.otherConcurrent systems
dc.subject.otherDesynchronization
dc.subject.otherElectronic design automation
dc.subject.otherHandshake protocols
dc.subject.otherSynthesis
dc.titleDesynchronization: Synthesis of asynchronous circuits from synchronous specifications
dc.typeArticle
dc.subject.lemacCircuits asíncrons
dc.subject.lemacCircuits integrats -- Disseny i construcció
dc.subject.lemacEstructura lògica
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/TCAD.2005.860958
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/1677680
dc.rights.accessOpen Access
local.identifier.drac1636570
dc.description.versionPostprint (published version)
local.citation.authorCortadella, J.; Kondratyev, A.; Lavagno, L.; Sotiriou, C.
local.citation.publicationNameIEEE transactions on computer-aided design of integrated circuits and systems
local.citation.volume25
local.citation.number10
local.citation.startingPage1904
local.citation.endingPage1921


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