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dc.contributor.authorVallero, Alessandro
dc.contributor.authorSavino, Alessandro
dc.contributor.authorChatzidimitriou, Athanansios
dc.contributor.authorKaliorakis, Manolis
dc.contributor.authorKooli, Maha
dc.contributor.authorRiera Villanueva, Marc
dc.contributor.authorDi Natale, Giorgio
dc.contributor.authorBosio, Alberto
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorGizopoulos, Dimitris
dc.contributor.authorDi Carlo, Stefano
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2019-01-09T16:24:15Z
dc.date.available2019-01-09T16:24:15Z
dc.date.issued2018-01-01
dc.identifier.citationVallero, A., Savino, A., Chatzidimitriou, A., Kaliorakis, M., Kooli, M., Riera, M., Di Natale, G., Bosio, A., Canal, R., Gizopoulos, D., S. D. C. SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems. "IEEE transactions on computers", 1 Gener 2018, vol. 68, núm. 5, p. 765-783.
dc.identifier.issn0018-9340
dc.identifier.urihttp://hdl.handle.net/2117/126429
dc.description© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractCross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal. Each system under analysis executes different software workloads both from benchmark suites and from real applications.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshMicroprocessors
dc.subject.otherReliability
dc.subject.otherCross-layer
dc.subject.otherMicroprocessors
dc.subject.otherSoft errors
dc.subject.otherFailures-in-Time
dc.titleSyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems
dc.typeArticle
dc.subject.lemacMicroprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.identifier.doi10.1109/TC.2018.2887225
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8580414
dc.rights.accessOpen Access
drac.iddocument23578766
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/611404/EU/Cross-Layer Early Reliability Evaluation for the Computing cOntinuum/CLERECO
upcommons.citation.authorVallero, A., Savino, A., Chatzidimitriou, A., Kaliorakis, M., Kooli, M., Riera, M., Di Natale, G., Bosio, A., Canal, R., Gizopoulos, D., Stefano Di Carlo
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on computers


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