SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
European Commisision's projectCLERECO - Cross-Layer Early Reliability Evaluation for the Computing cOntinuum (EC-FP7-611404)
Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal. Each system under analysis executes different software workloads both from benchmark suites and from real applications.
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CitationVallero, A., Savino, A., Chatzidimitriou, A., Kaliorakis, M., Kooli, M., Riera, M., Di Natale, G., Anglada, M., Bosio, A., Canal, R., González, A., Gizopoulos, D., Mariani, R., Di Carlo, S. SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems. "IEEE transactions on computers", 1 Gener 2018, vol. 68, núm. 5, p. 765-783.