Logic decomposition of speed-independent circuits
View/Open
Cita com:
hdl:2117/126062
Document typeArticle
Defense date1999-02
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial
property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public
communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: (1) logic decomposition of complex gates and (2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches and its effectiveness is evaluated by experiments on a set of benchmarks.
CitationKondratyev, A., Cortadella, J., Kishinevsky, M., Lavagno, L., Yakovlev, A. Logic decomposition of speed-independent circuits. "Proceedings of the IEEE", Febrer 1999, vol. 87, núm. 2, p. 347-362.
ISSN0018-9219
Publisher versionhttps://ieeexplore.ieee.org/document/740027
Files | Description | Size | Format | View |
---|---|---|---|---|
00740027.pdf | 435,4Kb | View/Open |