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dc.contributor.authorAmat Bertran, Esteve
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2018-12-19T09:52:54Z
dc.date.available2018-12-19T09:52:54Z
dc.date.issued2018
dc.identifier.citationAmat, E., Canal, R., Rubio, A. Modem gain-cell memories in advanced technologies. A: IEEE International Symposium on On-Line Testing and Robust System Design. "2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, (IOLTS 2018): 2–4 July 2018, Spain". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 65-68.
dc.identifier.isbn978-1-5386-5992-2
dc.identifier.urihttp://hdl.handle.net/2117/125975
dc.description.abstractWith the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- cells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT (i.e. sub-threshold).
dc.format.extent4 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits -- Reliability
dc.subject.otherDRAM
dc.subject.otherFinFET
dc.subject.otherGain-cells
dc.subject.otherSRAM
dc.subject.otherDynamic random access storage
dc.subject.otherSystems analysis
dc.subject.otherAdvanced technology
dc.subject.otherMemory cell
dc.subject.otherNon destructive
dc.subject.otherRead operation
dc.subject.otherReliability problems
dc.subject.otherSubthreshold
dc.subject.otherStatic random access storage
dc.titleModem gain-cell memories in advanced technologies
dc.typeConference report
dc.subject.lemacCircuits integrats -- Fiabilitat
dc.contributor.groupUniversitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/IOLTS.2018.8474151
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8474151
dc.rights.accessOpen Access
local.identifier.drac23540540
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TEC2016-75151-C3-2-R
local.citation.authorAmat, E.; Canal, R.; Rubio, A.
local.citation.contributorIEEE International Symposium on On-Line Testing and Robust System Design
local.citation.publicationName2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, (IOLTS 2018): 2–4 July 2018, Spain
local.citation.startingPage65
local.citation.endingPage68


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