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Modem gain-cell memories in advanced technologies
dc.contributor.author | Amat Bertran, Esteve |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2018-12-19T09:52:54Z |
dc.date.available | 2018-12-19T09:52:54Z |
dc.date.issued | 2018 |
dc.identifier.citation | Amat, E., Canal, R., Rubio, A. Modem gain-cell memories in advanced technologies. A: IEEE International Symposium on On-Line Testing and Robust System Design. "2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, (IOLTS 2018): 2–4 July 2018, Spain". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 65-68. |
dc.identifier.isbn | 978-1-5386-5992-2 |
dc.identifier.uri | http://hdl.handle.net/2117/125975 |
dc.description.abstract | With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- cells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT (i.e. sub-threshold). |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits -- Reliability |
dc.subject.other | DRAM |
dc.subject.other | FinFET |
dc.subject.other | Gain-cells |
dc.subject.other | SRAM |
dc.subject.other | Dynamic random access storage |
dc.subject.other | Systems analysis |
dc.subject.other | Advanced technology |
dc.subject.other | Memory cell |
dc.subject.other | Non destructive |
dc.subject.other | Read operation |
dc.subject.other | Reliability problems |
dc.subject.other | Subthreshold |
dc.subject.other | Static random access storage |
dc.title | Modem gain-cell memories in advanced technologies |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats -- Fiabilitat |
dc.contributor.group | Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/IOLTS.2018.8474151 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8474151 |
dc.rights.access | Open Access |
local.identifier.drac | 23540540 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/ |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO/1PE/TEC2016-75151-C3-2-R |
local.citation.author | Amat, E.; Canal, R.; Rubio, A. |
local.citation.contributor | IEEE International Symposium on On-Line Testing and Robust System Design |
local.citation.publicationName | 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, (IOLTS 2018): 2–4 July 2018, Spain |
local.citation.startingPage | 65 |
local.citation.endingPage | 68 |