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Enabling a reliable STT-MRAM main memory simulation

dc.contributor.authorAsifuzzaman, Kazi
dc.contributor.authorSánchez Verdejo, Rommel
dc.contributor.authorRadojković, Petar
dc.date.accessioned2018-11-22T11:03:10Z
dc.date.available2018-11-22T11:03:10Z
dc.date.issued2018-04-24
dc.identifier.citationAsifuzzaman, K.; Sánchez Verdejo, R.; Radojković, P. Enabling a reliable STT-MRAM main memory simulation. A: BSC Severo Ochoa International Doctoral Symposium (5th: 2018: Barcelona). "Book of abstracts". Barcelona: Barcelona Supercomputing Center, 2018, p. 22-23.
dc.identifier.urihttp://hdl.handle.net/2117/124892
dc.format.extent2 p.
dc.language.isoeng
dc.publisherBarcelona Supercomputing Center
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing
dc.subject.lcshComputer storage devices
dc.subject.otherSTT-MRAM
dc.subject.otherMain memory
dc.subject.otherHigh-performance computing
dc.titleEnabling a reliable STT-MRAM main memory simulation
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.subject.lemacOrdinadors -- Dispositius de memòria
dc.rights.accessOpen Access
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671578/EU/European Exascale Processor Memory Node Design/ExaNoDe
local.citation.contributorBSC Severo Ochoa International Doctoral Symposium (5th: 2018: Barcelona)
local.citation.pubplaceBarcelona
local.citation.publicationNameBook of abstracts
local.citation.startingPage22
local.citation.endingPage23


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